`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/11/05 18:02:13
// Design Name: 
// Module Name: data_ram_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module data_ram_tb();

    logic clka, ena;
    logic [10:0] addra;
    logic [31:0] dina;
    logic [31:0] douta;
    logic [3:0] wea;
    
    data_ram data (
        .clka(clka),
        .ena(ena),
        .addra(addra),
        .dina(dina),
        .douta(douta),
        .wea(wea)
    );
    
    always begin
        #10 clka = ~clka;
    end
    
    initial begin
    
        clka = 0; 
        ena = 0; 
        addra = 0;
        wea = 'b0000;
        
        #20 ena = 1; 
        #20 addra = 1;
        #20 addra = 2;
        #20 addra = 3;
        #20 addra = 4;

        #20 
        wea = 4'b0001;
        addra = 2;
        dina = 32'hffff_ffff;

        #20
        wea = 0;
        dina = 0;

        #20 
        wea = 4'b0100;
        addra = 2;
        dina = 32'hffff_ffff;

        #20
        wea = 0;
        dina = 0;

        
        #20 $finish;
    end
    
    
endmodule
